1. Field of the Invention
The present invention relates to an Analog-to-Digital (A/D) converter and a random-noise reducing method for A/D converters.
2. Description of the Related Art
It is desirable that A/D converters have a high Signal to Noise Ratio (SNR) indicative of a ratio between output signal power and noise power. In recent years, with a decrease in power-supply voltage due to microfabrication, it has become difficult to ensure a signal amplitude (signal power), thereby making it difficult to achieve a high SNR. For this reason, in particular, to sustain and further improve the SNR under low power-supply voltage, it is crucial how to reduce noise power.
As a method of reducing noise power, an example of technology is suggested in U.S. Pat. No. 7,312,734 in which two A/D converters are operated in parallel to average their outputs, thereby improving the SNR by 3 decibels. In this method, however, two A/D converters are used, thereby disadvantageously causing an increase in area occupancy and current consumption.
In another example of technology suggested in JP-A H07-312551 (KOKAI), A/D conversion is performed a plurality of times while an analog signal is held in a sample/hold circuit to average data obtained through these plural conversions. In this method, however, the sample/hold operation is performed by only one sample/hold circuit using one capacitative element. Therefore, even A/D conversion is performed a plurality of times on the held data, noise occurring at the sample/hold circuit and noise superposing on an input analog signal at the time of the sample/hold operation cannot be averaged. Since the noise occurring at the sample/hold circuit accounts for a large proportion with respect to SNR characteristics of the A/D converter, the incapability of reducing the noise by averaging is very problematic.